Module driver:x86apic - Generic Intel x86/IA32 local APIC driver
Generic Intel x86/IA32 local APIC driver. This driver provides support for the local APIC on Intel CPUs (or compatible).
Requires:
Used: driver:x86mp
Index
-
Group
APIC.ESR- Local APIC error register (ESR) bits-
Constant
APIC.ESR.ILLREG- Illegal register address (P4/Xeon/P6 only, not Pentium) -
Constant
APIC.ESR.RECVAE- Receive accept error (Pentium/P6 only, not P4/Xeon) -
Constant
APIC.ESR.RECVCSUM- Receive checksum error (Pentium/P6 only, not P4/Xeon) -
Constant
APIC.ESR.RECVIV- Receive illegal vector -
Constant
APIC.ESR.SENDAE- Send accept error (Pentium/P6 only, not P4/Xeon) -
Constant
APIC.ESR.SENDCSUM- Send checksum error (Pentium/P6 only, not P4/Xeon) -
Constant
APIC.ESR.SENDIV- Send illegal vector
-
Constant
-
Group
APIC.ICR0.DM- Local APIC ICR0 delivery-mode bits-
Constant
APIC.ICR0.DM.FIXED- Deliver specified vector to target processor(s) -
Constant
APIC.ICR0.DM.INIT- Deliver INIT to target processor(s), vector must be 0 -
Constant
APIC.ICR0.DM.LPRI- Deliver specified vector to lowest-priority processor (do not use) -
Constant
APIC.ICR0.DM.NMI- Deliver NMI to target processor(s), vector ignored -
Constant
APIC.ICR0.DM.SMI- Deliver SMI to target processor(s), vector must be 0 -
Constant
APIC.ICR0.DM.STUP- Deliver STARTUP to target processor(s), vector specifies address
-
Constant
-
Group
APIC.ICR0.DS- Local APIC ICR0 destination-shorthand bits-
Constant
APIC.ICR0.DS.AIS- Destination is all including self -
Constant
APIC.ICR0.DS.AXS- Destination is all excluding self -
Constant
APIC.ICR0.DS.NS- No destination shorthand (as specified in dest field) -
Constant
APIC.ICR0.DS.SELF- Destination is self
-
Constant
-
Record
APIC.IPI.DISPATCH- Structure used for dispatching interprocessor interrupts (IPIs)-
Variable
apic.id- Target APIC ID (physical) -
Variable
dmode- Delivery mode constant -
Variable
vector- Vector to trigger (address for STUP) -
Variable
wait- If TRUE , wait for IPI to finish (polled)
-
Variable
-
Group
APIC.LVT- Local APIC local vector table (LVT) register bits-
Constant
APIC.LVT.DM.MASK- Delivery mode mask (LVT.LINT, LVT.TS, LVT.PMC only) -
Constant
APIC.LVT.DM.SHIFT- Delivery mode shift (LVT.LINT, LVT.TS, LVT.PMC only) -
Constant
APIC.LVT.DST.PENDING- Delivery status send pending -
Constant
APIC.LVT.LINT.PINPOL- Input pin polarity (LVT.LINT only) -
Constant
APIC.LVT.LINT.RIRR- Remote IRR (LVT.LINT only) -
Constant
APIC.LVT.LINT.TLVL- Level, else edge, trigger mode (LVT.LINT only) -
Constant
APIC.LVT.MASKED- Vector is masked (not delivered) -
Constant
APIC.LVT.TMR.PERIOD- Timer-mode perodic, else one-shot (LVT.TMR only) -
Constant
APIC.LVT.VECTOR.MASK- Delivery vector mask
-
Constant
-
Group
APIC.LVT.DM- Local APIC local vector table (LVT) delivery-mode bits-
Constant
APIC.LVT.DM.EXTINT- Deliver pretend 8259A-compatible interrupt (INTA line), -
Constant
APIC.LVT.DM.FIXED- Deliver interrupt specified in vector field -
Constant
APIC.LVT.DM.INIT- Deliver INIT request to processor, vector must be 0 -
Constant
APIC.LVT.DM.NMI- Deliver NMI interrupt to processor, vector ignored -
Constant
APIC.LVT.DM.SMI- Deliver SMI interrupt to processor, vector must be 0
-
Constant
-
Group
APIC.REG- Local APIC registers-
Constant
APIC.REG.APR- arbitration priority (r/o) -
Constant
APIC.REG.DRF- destination register format (bits 0:27 r/o, 28-31 r/w) -
Constant
APIC.REG.EOI- end of interrupt (?) (w/o) -
Constant
APIC.REG.ESR- error status (r/o) -
Constant
APIC.REG.ICR0- interrupt-command (bits 0:31 r/w) -
Constant
APIC.REG.ICR1- interrupt-command (bits 32:63 r/w) -
Constant
APIC.REG.ID- APIC ID (r/w) -
Constant
APIC.REG.IRR0- interrupt-request (bits 0:31 r/o) -
Constant
APIC.REG.IRR1- interrupt-request (bits 32:63 r/o) -
Constant
APIC.REG.IRR2- interrupt-request (bits 64:95 r/o) -
Constant
APIC.REG.IRR3- interrupt-request (bits 96:127 r/o) -
Constant
APIC.REG.IRR4- interrupt-request (bits 128:159 r/o) -
Constant
APIC.REG.IRR5- interrupt-request (bits 160:191 r/o) -
Constant
APIC.REG.IRR6- interrupt-request (bits 192:223 r/o) -
Constant
APIC.REG.IRR7- interrupt-request (bits 224:255 r/o) -
Constant
APIC.REG.ISR0- in-service (bits 0:31 r/o) -
Constant
APIC.REG.ISR1- in-service (bits 32:63 r/o) -
Constant
APIC.REG.ISR2- in-service (bits 64:95 r/o) -
Constant
APIC.REG.ISR3- in-service (bits 96:127 r/o) -
Constant
APIC.REG.ISR4- in-service (bits 128:159 r/o) -
Constant
APIC.REG.ISR5- in-service (bits 160:191 r/o) -
Constant
APIC.REG.ISR6- in-service (bits 192:223 r/o) -
Constant
APIC.REG.ISR7- in-service (bits 224:255 r/o) -
Constant
APIC.REG.LDR- logical destination register (r/w) -
Constant
APIC.REG.LVT.CMCI- LVT CMCI (r/w) -
Constant
APIC.REG.LVT.ERR- LVT error (r/w) -
Constant
APIC.REG.LVT.LINT0- LVT LINT0 (r/w) -
Constant
APIC.REG.LVT.LINT1- LVT LINT1 (r/w) -
Constant
APIC.REG.LVT.PMC- LVT performance monitoring counters (r/w) -
Constant
APIC.REG.LVT.TMR- LVT timer (r/w) -
Constant
APIC.REG.LVT.TS- LVT thermal sensor (r/w) -
Constant
APIC.REG.PPR- processor priority (r/o) -
Constant
APIC.REG.SI- spurious interrupt vector (bits 0:8 r/w, 9-31 r/o) -
Constant
APIC.REG.TMR.CCR- timer current count (r/o) -
Constant
APIC.REG.TMR.DIVR- timer divide configuration (r/w) -
Constant
APIC.REG.TMR.ICR- timer initial count (r/w) -
Constant
APIC.REG.TMR0- trigger-mode (bits 0:31 r/o) -
Constant
APIC.REG.TMR1- trigger-mode (bits 32:63 r/o) -
Constant
APIC.REG.TMR2- trigger-mode (bits 64:95 r/o) -
Constant
APIC.REG.TMR3- trigger-mode (bits 96:127 r/o) -
Constant
APIC.REG.TMR4- trigger-mode (bits 128:159 r/o) -
Constant
APIC.REG.TMR5- trigger-mode (bits 160:191 r/o) -
Constant
APIC.REG.TMR6- trigger-mode (bits 192:223 r/o) -
Constant
APIC.REG.TMR7- trigger-mode (bits 224:255 r/o) -
Constant
APIC.REG.TPR- task priority (r/w) -
Constant
APIC.REG.VER- APIC version (r/o)
-
Constant
-
Record
APIC.TIMER.SET- Structure used for setting the APIC timer-
Variable
divisor- Timer divisor (from core frequency, ) -
Variable
oneshot- One-shot mode, or repeating -
Variable
value- Initial value for the countdown -
Variable
vector- Interrupt vector (0-255)
-
Variable
-
Group
APIC.TMR.DIVR- Local APIC timer divisor values -
Channel type
CT.APIC- APIC channel-type-
Variable
in?- Commands in -
Variable
out!- Responses out -
Variable
return?- Used to close the connection to, and shut-down, the APIC
-
Variable
-
Protocol
P.APIC.IN- APIC input protocol-
Tag
cancel.timer- Cancels a running timer -
Tag
disable- Disable the APIC -
Tag
dispatch.clear- Clear pending IPI dispatch -
Tag
dispatch.done- Test for IPI dispatch complete, returns in 'result' -
Tag
dispatch.ipi- Dispatch interprocessor interrupt -
Tag
enable- Enable the APIC -
Tag
get.apic.id- Reads the APIC ID -
Tag
get.apic.version- Reads the APIC version -
Tag
get.error- Get APIC error flags, returns in 'result' -
Tag
init- Initialise APIC -
Tag
reset.error- Resets APIC error flags -
Tag
set.timer- Sets the timer to go off
-
Tag
-
Protocol
P.APIC.OUT- APIC output protocol-
Tag
apic.id- APIC ID result -
Tag
apic.version- APIC version result -
Tag
result- Generic result
-
Tag
-
Process
x86apic.driver- x86 multiprocessor local APIC driver
Declarations
x86apic.inc:40Group APIC.REG
Local APIC registers
x86apic.inc:41Constant APIC.REG.ID
VAL INT32 APIC.REG.ID
APIC ID (r/w)
x86apic.inc:42Constant APIC.REG.VER
VAL INT32 APIC.REG.VER
APIC version (r/o)
x86apic.inc:43Constant APIC.REG.TPR
VAL INT32 APIC.REG.TPR
task priority (r/w)
x86apic.inc:44Constant APIC.REG.APR
VAL INT32 APIC.REG.APR
arbitration priority (r/o)
x86apic.inc:45Constant APIC.REG.PPR
VAL INT32 APIC.REG.PPR
processor priority (r/o)
x86apic.inc:46Constant APIC.REG.EOI
VAL INT32 APIC.REG.EOI
end of interrupt (?) (w/o)
x86apic.inc:47Constant APIC.REG.LDR
VAL INT32 APIC.REG.LDR
logical destination register (r/w)
x86apic.inc:48Constant APIC.REG.DRF
VAL INT32 APIC.REG.DRF
destination register format (bits 0:27 r/o, 28-31 r/w)
x86apic.inc:49Constant APIC.REG.SI
VAL INT32 APIC.REG.SI
spurious interrupt vector (bits 0:8 r/w, 9-31 r/o)
x86apic.inc:50Constant APIC.REG.ISR0
VAL INT32 APIC.REG.ISR0
in-service (bits 0:31 r/o)
x86apic.inc:51Constant APIC.REG.ISR1
VAL INT32 APIC.REG.ISR1
in-service (bits 32:63 r/o)
x86apic.inc:52Constant APIC.REG.ISR2
VAL INT32 APIC.REG.ISR2
in-service (bits 64:95 r/o)
x86apic.inc:53Constant APIC.REG.ISR3
VAL INT32 APIC.REG.ISR3
in-service (bits 96:127 r/o)
x86apic.inc:54Constant APIC.REG.ISR4
VAL INT32 APIC.REG.ISR4
in-service (bits 128:159 r/o)
x86apic.inc:55Constant APIC.REG.ISR5
VAL INT32 APIC.REG.ISR5
in-service (bits 160:191 r/o)
x86apic.inc:56Constant APIC.REG.ISR6
VAL INT32 APIC.REG.ISR6
in-service (bits 192:223 r/o)
x86apic.inc:57Constant APIC.REG.ISR7
VAL INT32 APIC.REG.ISR7
in-service (bits 224:255 r/o)
x86apic.inc:58Constant APIC.REG.TMR0
VAL INT32 APIC.REG.TMR0
trigger-mode (bits 0:31 r/o)
x86apic.inc:59Constant APIC.REG.TMR1
VAL INT32 APIC.REG.TMR1
trigger-mode (bits 32:63 r/o)
x86apic.inc:60Constant APIC.REG.TMR2
VAL INT32 APIC.REG.TMR2
trigger-mode (bits 64:95 r/o)
x86apic.inc:61Constant APIC.REG.TMR3
VAL INT32 APIC.REG.TMR3
trigger-mode (bits 96:127 r/o)
x86apic.inc:62Constant APIC.REG.TMR4
VAL INT32 APIC.REG.TMR4
trigger-mode (bits 128:159 r/o)
x86apic.inc:63Constant APIC.REG.TMR5
VAL INT32 APIC.REG.TMR5
trigger-mode (bits 160:191 r/o)
x86apic.inc:64Constant APIC.REG.TMR6
VAL INT32 APIC.REG.TMR6
trigger-mode (bits 192:223 r/o)
x86apic.inc:65Constant APIC.REG.TMR7
VAL INT32 APIC.REG.TMR7
trigger-mode (bits 224:255 r/o)
x86apic.inc:66Constant APIC.REG.IRR0
VAL INT32 APIC.REG.IRR0
interrupt-request (bits 0:31 r/o)
x86apic.inc:67Constant APIC.REG.IRR1
VAL INT32 APIC.REG.IRR1
interrupt-request (bits 32:63 r/o)
x86apic.inc:68Constant APIC.REG.IRR2
VAL INT32 APIC.REG.IRR2
interrupt-request (bits 64:95 r/o)
x86apic.inc:69Constant APIC.REG.IRR3
VAL INT32 APIC.REG.IRR3
interrupt-request (bits 96:127 r/o)
x86apic.inc:70Constant APIC.REG.IRR4
VAL INT32 APIC.REG.IRR4
interrupt-request (bits 128:159 r/o)
x86apic.inc:71Constant APIC.REG.IRR5
VAL INT32 APIC.REG.IRR5
interrupt-request (bits 160:191 r/o)
x86apic.inc:72Constant APIC.REG.IRR6
VAL INT32 APIC.REG.IRR6
interrupt-request (bits 192:223 r/o)
x86apic.inc:73Constant APIC.REG.IRR7
VAL INT32 APIC.REG.IRR7
interrupt-request (bits 224:255 r/o)
x86apic.inc:74Constant APIC.REG.ESR
VAL INT32 APIC.REG.ESR
error status (r/o)
x86apic.inc:75Constant APIC.REG.LVT.CMCI
VAL INT32 APIC.REG.LVT.CMCI
LVT CMCI (r/w)
x86apic.inc:76Constant APIC.REG.ICR0
VAL INT32 APIC.REG.ICR0
interrupt-command (bits 0:31 r/w)
x86apic.inc:77Constant APIC.REG.ICR1
VAL INT32 APIC.REG.ICR1
interrupt-command (bits 32:63 r/w)
x86apic.inc:78Constant APIC.REG.LVT.TMR
VAL INT32 APIC.REG.LVT.TMR
LVT timer (r/w)
x86apic.inc:79Constant APIC.REG.LVT.TS
VAL INT32 APIC.REG.LVT.TS
LVT thermal sensor (r/w)
x86apic.inc:80Constant APIC.REG.LVT.PMC
VAL INT32 APIC.REG.LVT.PMC
LVT performance monitoring counters (r/w)
x86apic.inc:81Constant APIC.REG.LVT.LINT0
VAL INT32 APIC.REG.LVT.LINT0
LVT LINT0 (r/w)
x86apic.inc:82Constant APIC.REG.LVT.LINT1
VAL INT32 APIC.REG.LVT.LINT1
LVT LINT1 (r/w)
x86apic.inc:83Constant APIC.REG.LVT.ERR
VAL INT32 APIC.REG.LVT.ERR
LVT error (r/w)
x86apic.inc:84Constant APIC.REG.TMR.ICR
VAL INT32 APIC.REG.TMR.ICR
timer initial count (r/w)
x86apic.inc:85Constant APIC.REG.TMR.CCR
VAL INT32 APIC.REG.TMR.CCR
timer current count (r/o)
x86apic.inc:86Constant APIC.REG.TMR.DIVR
VAL INT32 APIC.REG.TMR.DIVR
timer divide configuration (r/w)
x86apic.inc:96Group APIC.ICR0.DM
Local APIC ICR0 delivery-mode bits.
x86apic.inc:97Constant APIC.ICR0.DM.FIXED
VAL INT32 APIC.ICR0.DM.FIXED
Deliver specified vector to target processor(s).
x86apic.inc:98Constant APIC.ICR0.DM.LPRI
VAL INT32 APIC.ICR0.DM.LPRI
Deliver specified vector to lowest-priority processor (do not use).
x86apic.inc:99Constant APIC.ICR0.DM.SMI
VAL INT32 APIC.ICR0.DM.SMI
Deliver SMI to target processor(s), vector must be 0.
x86apic.inc:100Constant APIC.ICR0.DM.NMI
VAL INT32 APIC.ICR0.DM.NMI
Deliver NMI to target processor(s), vector ignored.
x86apic.inc:101Constant APIC.ICR0.DM.INIT
VAL INT32 APIC.ICR0.DM.INIT
Deliver INIT to target processor(s), vector must be 0.
x86apic.inc:102Constant APIC.ICR0.DM.STUP
VAL INT32 APIC.ICR0.DM.STUP
Deliver STARTUP to target processor(s), vector specifies address.
x86apic.inc:111Group APIC.ICR0.DS
Local APIC ICR0 destination-shorthand bits.
x86apic.inc:112Constant APIC.ICR0.DS.NS
VAL INT32 APIC.ICR0.DS.NS
No destination shorthand (as specified in dest field).
x86apic.inc:113Constant APIC.ICR0.DS.SELF
VAL INT32 APIC.ICR0.DS.SELF
Destination is self.
x86apic.inc:114Constant APIC.ICR0.DS.AIS
VAL INT32 APIC.ICR0.DS.AIS
Destination is all including self.
x86apic.inc:115Constant APIC.ICR0.DS.AXS
VAL INT32 APIC.ICR0.DS.AXS
Destination is all excluding self.
x86apic.inc:121Group APIC.LVT
Local APIC local vector table (LVT) register bits. Default hardware state for these is #00010000 (masked).
x86apic.inc:124Constant APIC.LVT.TMR.PERIOD
VAL INT32 APIC.LVT.TMR.PERIOD
Timer-mode perodic, else one-shot (LVT.TMR only).
x86apic.inc:125Constant APIC.LVT.MASKED
VAL INT32 APIC.LVT.MASKED
Vector is masked (not delivered).
x86apic.inc:126Constant APIC.LVT.LINT.TLVL
VAL INT32 APIC.LVT.LINT.TLVL
Level, else edge, trigger mode (LVT.LINT only).
x86apic.inc:127Constant APIC.LVT.LINT.RIRR
VAL INT32 APIC.LVT.LINT.RIRR
Remote IRR (LVT.LINT only).
x86apic.inc:128Constant APIC.LVT.LINT.PINPOL
VAL INT32 APIC.LVT.LINT.PINPOL
Input pin polarity (LVT.LINT only).
x86apic.inc:129Constant APIC.LVT.DST.PENDING
VAL INT32 APIC.LVT.DST.PENDING
Delivery status send pending.
x86apic.inc:130Constant APIC.LVT.DM.MASK
VAL INT32 APIC.LVT.DM.MASK
Delivery mode mask (LVT.LINT, LVT.TS, LVT.PMC only).
x86apic.inc:131Constant APIC.LVT.DM.SHIFT
VAL INT APIC.LVT.DM.SHIFT
Delivery mode shift (LVT.LINT, LVT.TS, LVT.PMC only).
x86apic.inc:132Constant APIC.LVT.VECTOR.MASK
VAL INT32 APIC.LVT.VECTOR.MASK
Delivery vector mask.
x86apic.inc:134Group APIC.LVT.DM
Local APIC local vector table (LVT) delivery-mode bits.
x86apic.inc:135Constant APIC.LVT.DM.FIXED
VAL INT32 APIC.LVT.DM.FIXED
Deliver interrupt specified in vector field.
x86apic.inc:136Constant APIC.LVT.DM.SMI
VAL INT32 APIC.LVT.DM.SMI
Deliver SMI interrupt to processor, vector must be 0.
x86apic.inc:137Constant APIC.LVT.DM.NMI
VAL INT32 APIC.LVT.DM.NMI
Deliver NMI interrupt to processor, vector ignored.
x86apic.inc:138Constant APIC.LVT.DM.INIT
VAL INT32 APIC.LVT.DM.INIT
Deliver INIT request to processor, vector must be 0.
x86apic.inc:139Constant APIC.LVT.DM.EXTINT
VAL INT32 APIC.LVT.DM.EXTINT
Deliver pretend 8259A-compatible interrupt (INTA line),
x86apic.inc:142Group APIC.ESR
Local APIC error register (ESR) bits.
x86apic.inc:143Constant APIC.ESR.SENDCSUM
VAL INT32 APIC.ESR.SENDCSUM
Send checksum error (Pentium/P6 only, not P4/Xeon).
x86apic.inc:144Constant APIC.ESR.RECVCSUM
VAL INT32 APIC.ESR.RECVCSUM
Receive checksum error (Pentium/P6 only, not P4/Xeon).
x86apic.inc:145Constant APIC.ESR.SENDAE
VAL INT32 APIC.ESR.SENDAE
Send accept error (Pentium/P6 only, not P4/Xeon).
x86apic.inc:146Constant APIC.ESR.RECVAE
VAL INT32 APIC.ESR.RECVAE
Receive accept error (Pentium/P6 only, not P4/Xeon).
x86apic.inc:147Constant APIC.ESR.SENDIV
VAL INT32 APIC.ESR.SENDIV
Send illegal vector.
x86apic.inc:148Constant APIC.ESR.RECVIV
VAL INT32 APIC.ESR.RECVIV
Receive illegal vector.
x86apic.inc:149Constant APIC.ESR.ILLREG
VAL INT32 APIC.ESR.ILLREG
Illegal register address (P4/Xeon/P6 only, not Pentium).
x86apic.inc:151Group APIC.TMR.DIVR
Local APIC timer divisor values
x86apic.inc:164Record APIC.IPI.DISPATCH
DATA TYPE APIC.IPI.DISPATCH
Structure used for dispatching interprocessor interrupts (IPIs).
x86apic.inc:166Variable dmode
INT32
Delivery mode constant.
x86apic.inc:167Variable apic.id
BYTE
Target APIC ID (physical).
x86apic.inc:168Variable vector
BYTE
Vector to trigger (address for STUP).
x86apic.inc:169Variable wait
BOOL
If TRUE, wait for IPI to finish (polled)
x86apic.inc:173Record APIC.TIMER.SET
DATA TYPE APIC.TIMER.SET
Structure used for setting the APIC timer.
x86apic.inc:182Protocol P.APIC.IN
PROTOCOL P.APIC.IN
APIC input protocol.
x86apic.inc:187Tag init
init; INT32; INT
Initialise APIC.
Parameters:
INT32 |
addr |
Physical address of the APIC memory (4k). |
INT |
aff |
Scheduler affinity setting. |
x86apic.inc:188Tag get.apic.id
get.apic.id
Reads the APIC ID.
x86apic.inc:189Tag get.apic.version
get.apic.version
Reads the APIC version.
x86apic.inc:190Tag enable
enable
Enable the APIC.
x86apic.inc:191Tag disable
disable
Disable the APIC.
x86apic.inc:192Tag dispatch.ipi
dispatch.ipi; APIC.IPI.DISPATCH
Dispatch interprocessor interrupt.
x86apic.inc:193Tag dispatch.done
dispatch.done
Test for IPI dispatch complete, returns in 'result'.
x86apic.inc:194Tag dispatch.clear
dispatch.clear
Clear pending IPI dispatch.
x86apic.inc:195Tag get.error
get.error
Get APIC error flags, returns in 'result'.
x86apic.inc:196Tag reset.error
reset.error
Resets APIC error flags.
x86apic.inc:197Tag set.timer
set.timer; APIC.TIMER.SET
Sets the timer to go off.
x86apic.inc:198Tag cancel.timer
cancel.timer
Cancels a running timer.
x86apic.inc:201Protocol P.APIC.OUT
PROTOCOL P.APIC.OUT
APIC output protocol.
x86apic.inc:205Tag result
result; INT
Generic result.
Parameters:
INT |
val |
Return value or error. |
x86apic.inc:206Tag apic.id
apic.id; BYTE
APIC ID result.
x86apic.inc:210Tag apic.version
apic.version; BYTE; INT
APIC version result.
Parameters:
BYTE |
ver |
Version byte (#1x = local APIC, #0x = external APIC). |
INT |
lvt |
Entries in local vector table. |
x86apic.inc:213Channel type CT.APIC
RECURSIVE CHAN TYPE CT.APIC
APIC channel-type
x86apic.inc:215Variable in?
CHAN P.APIC.IN
Commands in.
x86apic.inc:216Variable out!
CHAN P.APIC.OUT
Responses out.
x86apic.inc:217Variable return?
CHAN CT.APIC!
Used to close the connection to, and shut-down, the APIC.
x86apic.occ:64Process x86apic.driver
PROC x86apic.driver (CT.DRIVER? link, SHARED LOG! log, VAL []BYTE options)
x86 multiprocessor local APIC driver.
This provides support for a standard Intel APIC, used for interrupt routing and multiprocessor control/signalling.
Parameters:
CT.DRIVER? |
link |
Connection to parent driver (server). |
SHARED LOG! |
log |
System log channels. |
VAL []BYTE |
options |
Driver options. |